“Flash plus logic” integration refers to flash memory and logic, such as a static random access memory (SRAM) cells and/or transistors, formed on a shared substrate. Flash memory may typically have wordlines and bitlines to access flash memory cells. SRAM may also have wordlines and bitlines. A transistor may have a source, a gate and a drain.
A flash plus logic fabrication process may use a “pattern registration” model, which is described on pages 273–274 in “Lithography” in VLSI Technology by D. A. McGillis published in 1983. The pattern registration model is commonly used in many semiconductor planar processes. In a mask alignment scheme of a typical semiconductor planar process, “registration” refers to a process and/or accuracy of an upper masking layer aligning to an underlining mask layer. The underlining mask layer is called a “registered” layer and is formed before the upper “registering” mask layer.